`timescale 1ns / 1ps
`include "defines2.vh"
module mul(input wire [31:0] a,
            input wire [31:0] b,
            input wire [5:0] op, // 判断是否有符号
            output reg [63:0] y
            );
wire[31:0]mult_a,mult_b;
wire[63:0]hilo_temp;
//判断乘数和被乘数的符号
assign mult_a = ((op==`MULT_CONTROL) && (a[31]==1'b1))? (~a+1) :a;
assign mult_b = ((op==`MULT_CONTROL) && (b[31]==1'b1))? (~b+1) :b;

assign hilo_temp = ((op==`MULT_CONTROL) && (a[31]^b[31])) ? ~(mult_a * mult_b)+1 : mult_a * mult_b;
 
always @(*) begin
    case (op)
        `MULT: y <= hilo_temp;
        `MULTU: y <= hilo_temp;
        default: y <= 64'b0;
    endcase
end

endmodule
